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1
Примеры проектирования цифровых устройств с использованием языков описания аппаратуры
Стешенко В.
next_state
reset
std_logic
clk
mux_out
input
data_out
output
data_in
enable
vhdl
verilog
downto
st0
std_logic_vector
architecture
port
endmodule
library
module
st4
ieee.std_logic_1164
pres_state
yout
behav
endcase
preset
mux
fsm
st3
clock
st2
gate
width
behave
elsif
posedge
pout
shift
clk’event
mpumep
onucahua
abtomata
count
софт
equality
moore
muxout
outputs
b00
Language:
russian
File:
ZIP, 393 KB
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