Fundraising September 15, 2024 – October 1, 2024
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1
FPGA时序约束与分析
吴厚航
钟
clock
path
delay
延
fpga
析
沿
edge
setup
uncertainty
虚
routed
timing
默
input
衍
芯
period
required
false
slack
destination
get_ports
summary
频
0.000ns
arrival
fdre
锁
output
cnt_reg
pcb
get_pins
command
抖
report
requirement
域
辑
rising
paths
set_output_delay
constraints
拟
000ns
get_clocks
5ns
jitter
skew
Year:
2022
Language:
chinese
File:
PDF, 56.22 MB
Your tags:
5.0
/
5.0
chinese, 2022
2
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
Springer-Verlag New York
Sridhar Gangadharan
,
Sanjay Churiwala (auth.)
clock
timing
constraints
path
clocks
delay
specified
edge
input
analysis
paths
output
sdc
setup
period
signal
get_ports
port
command
generated
circuit
flop
specify
synthesis
tools
chip
transition
clk
consider
commands
option
network
latency
specific
false
cycle
capture
check
combinational
create_clock
delays
set_input_delay
tcl
waveform
launch
specification
modes
required
negative
shown
Year:
2013
Language:
english
File:
PDF, 3.27 MB
Your tags:
5.0
/
5.0
english, 2013
3
Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)
Springer-Verlag New York
Sridhar Gangadharan
,
Sanjay Churiwala (auth.)
clock
timing
constraints
path
clocks
delay
specified
edge
input
analysis
paths
output
sdc
setup
period
signal
get_ports
port
command
generated
circuit
flop
specify
synthesis
tools
chip
transition
clk
consider
commands
option
network
latency
specific
false
cycle
capture
check
combinational
create_clock
delays
set_input_delay
tcl
waveform
launch
specification
modes
required
negative
shown
Year:
2013
Language:
english
File:
PDF, 8.58 MB
Your tags:
5.0
/
5.0
english, 2013
4
FPGA设计 从电路到系统
北京:清华大学出版社
Pdg2Pic
,
蔡述庭,陈平,棠潮等编著
fpga
input
clk
verilog
hdl
output
module
endmodule
reset
signed
o_result
clock
mux8
rst_n
out_seq
next_state
i_b
posedge
altera
i_add_sub
xilinx
mealy
i_a
in_seq
initial
latch
moore
synplify
assign
bes
soc
add_sub
i_rst_n
iit
parameter
rea
synopsys
enable
get_clocks
library
setup
all_inputs
brr
cirq
clb
nios
cyclone
datawidth
dsp
fea
Year:
2014
Language:
Chinese
File:
PDF, 62.98 MB
Your tags:
0
/
0
Chinese, 2014
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