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1
Hybrid CMOS Single-Electron-Transistor Device and Circuit Design
Adrian Mihai Ionescu Santanu Mahapatra [Santanu Mahapatra
,
Adrian Mihai Ionescu]
figure
electron
cmos
device
gate
current
circuit
hybrid
transistor
drain
voltage
temperature
mosfet
setmos
sets
silicon
devices
tunneling
coulomb
inverter
blockade
memory
architecture
bias
technology
output
tunnel
fabrication
vds
input
mib
circuits
effect
shown
ndr
vgs
parameters
simulation
dissipation
capacitance
operation
valued
transistors
binary
quaternary
modeling
schematic
proposed
static
analog
Year:
2006
Language:
spanish
File:
AZW3 , 9.15 MB
Your tags:
0
/
0
spanish, 2006
2
Hybrid CMOS Single-electron-transistor Device and Circuit Design
Artech House Publishers
Santanu Mahapatra
,
Adrian M. Ionescu
figure
electron
cmos
device
gate
current
circuit
hybrid
transistor
drain
voltage
temperature
mosfet
setmos
sets
silicon
devices
tunneling
coulomb
inverter
blockade
memory
architecture
bias
technology
output
tunnel
vds
input
fabrication
circuits
mib
effect
shown
ndr
vgs
parameters
simulation
dissipation
capacitance
operation
valued
binary
transistors
quaternary
schematic
proposed
static
analog
modeling
Year:
2006
Language:
english
File:
TXT, 373 KB
Your tags:
0
/
0
english, 2006
3
Hybrid CMOS Single-Electron-Transistor Device and Circuit Design
Santanu Mahapatra
,
Adrian Mihai Ionescu [Santanu Mahapatra
,
Adrian Mihai Ionescu]
figure
cmos
electron
device
gate
current
circuit
hybrid
voltage
transistor
drain
vds
temperature
mosfet
setmos
sets
silicon
devices
tunneling
coulomb
vgs
inverter
blockade
memory
architecture
technology
output
tunnel
vout
input
circuits
cσ
ibias
mib
effect
shown
fabrication
ndr
parameters
simulation
dissipation
capacitance
operation
γs
vdd
binary
transistors
valued
schematic
proposed
Year:
2006
Language:
spanish
File:
PDF, 8.48 MB
Your tags:
0
/
0
spanish, 2006
4
Hybrid CMOS Single-Electron-Transistor Device And Circuit Design
Artech House
Santanu Mahapatra
,
Adrian Mihai Ionescu
figure
cmos
electron
device
gate
current
circuit
hybrid
voltage
transistor
drain
vds
temperature
mosfet
setmos
sets
silicon
devices
tunneling
coulomb
vgs
inverter
blockade
memory
architecture
technology
output
tunnel
vout
input
circuits
cσ
ibias
mib
effect
shown
fabrication
ndr
parameters
simulation
dissipation
capacitance
operation
γs
vdd
binary
transistors
valued
schematic
proposed
Year:
2006
Language:
english
File:
PDF, 8.47 MB
Your tags:
0
/
0
english, 2006
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